1. PCI2050B features
support two 32-bit, 66-MHz PCI buses;
             CompactPCI hot-swap functionality;

can be used to overcome the electrical loading limits of 10 devices per PCI bus.

provides internal arbitration for nine possible secondary bus masters,
and provides each with a dedicated active low request/grant pair (/REG//GNT).

CompactPCI backplane needs 7 peripheral slots.

The PCI configuration header of the bridge is only accessible from the primary PCI interface;

66-MHz operation:(Terminals: CONFIG66, P_M66ENA, S_M66ENA)
66-MHz primary bus; 66-MHz secondary bus;
66-MHz primary bus; 33-MHz secondary bus;
33-MHz primary bus; 33-MHz secondary bus;

2. 路由分析

PCI拓扑，采用深度优先搜索算法，即先进行深度优先映射，然后再进行广度优先映射。

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